Photolithography process is critical to the fabrication of semiconductor devices because it allows transferring a series of circuit patterns from photomasks to corresponding ties of chip dies on a wafer through exposure. It is considered as a core step in the manufacturing of large-scale integrated circuits, and a wide range of complex and time-consuming photolithography processes in the fabrication of semiconductor devices are accomplished by suitable photolithography machines.
A photolithography machine incorporates a wafer stage which is configured mainly to support a wafer and carry it to move under a projection objective in coordination with a mask stage so that the wafer is exposed in a desired way. When the wafer and mask stages are moving within an internal frame of the machine, reaction forces resulting from the movement will directly act on the internal frame and may intensify its vibration. If the magnitude of the vibration is too large to satisfy a corresponding performance constraint of the system, satisfactory exposure would not be attained any longer.
In one solution proposed in the prior art for this problem, the stator of a motor for the motion stages is disposed on an external frame so that the reaction forces generated from the movement of the motion stages during exposure directly act on the external frame instead of the internal. This solution, however, is highly demanding on the structural design of the frames and motion stages and tends to increase the complexity of integration of the motion stages into the system.
There are also proposed in the prior art a device for compensating for a reaction force from a motion stage and a photolithography machine in which such devices are incorporated in direct connection with an internal frame. However, due to absence of decoupling mechanisms between the motion stages and shock absorbers, vibration from the ground tends to be introduced during operation of the system, which may pose a direct impact on movement accuracy of the motion stages. In addition, the reaction force compensation devices, deployed on both sides of the wafer stage, have a large footprint which is unfavorable to the layout and maintenance of other subsystems.